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TDA7440D tone control digitally controlled audio processor input multiplexer - 4 stereo inputs - selectable input gain for optimal adaptation to different sources one stereo output treble and bass control in 2.0db steps volume control in 1.0db steps two speaker attenuators: - two independent speaker control in 1.0db steps for balance facility - independent mute function all function are programmable via serial bus description the TDA7440D is a volume tone (bass and treble) balance (left/right) processor for quality audio applications in hi-fi systems. selectable input gain is provided. control of all the functions is accomplished by serial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained april 1999 ? 0/30db 2db step muxoutl inl volume volume treble treble treble(l) muxoutr inr treble(r) bout(l) spkr att left lout scl sda dig_gnd rout d98au883 i 2 cbus decoder + latches 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 g input multiplexer + gain bass bin(l) bass spkr att right bout(r) bin(r) supply cref agnd v s 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 10 11 19 12 13 23 8 9 18 14 15 r b r b v ref block diagram ordering number: TDA7440D so28 1/16
absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temperature -10 to 85 c t stg storage temperature range -55 to 150 c thermal data symbol parameter value unit r th j-pin thermal resistance junction-pins 85 c/w l_in3 l_in4 muxoutl in(l) muxout(r) bin(r) in(r) bout(r) bin(l) 1 3 2 4 5 6 7 8 9 bout(l) n.c. n.c. treble(r) treble(l) scl sda dig-gnd cref 23 22 21 20 19 17 18 16 15 d98au884 10 11 12 13 14 28 27 26 25 24 r_in3 r_in2 r_in1 l_in1 l_in2 v s agnd rout lout r_in4 pin connection (top view) quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db input gain in (2db step) 0 30 db volume control (1db step) -47 0 db treble control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step -79 0 db mute attenuation 100 db TDA7440D 2/16
electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , r g = 600 w , all controls flat (g = 0db), unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10.2 v i s supply current 4 7 10 ma svr ripple rejection 60 90 db input stage r in input resistance 70 100 130 k w v cl clipping level thd = 0.3% 2 2.5 vrms s in input separation the selected input is grounded through a 2.2 m capacitor 80 100 db g inmin minimum input gain -1 0 1 db g inman maximum input gain 29 30 31 db g step step resolution 1.5 2 2.5 db volume control r i input resistance 20 33 50 k w c range control range 45 47 49 db a vmax max. attenuation 45 47 49 db a step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -24db -1.0 0 1.0 db a v = -24 to -47db -1.5 0 1.5 db e t tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db v dc dc step adjacent attenuation steps from 0db to a v max 0 0.5 3mv mv a mute mute attenuation 80 100 db bass control (1) gb control range max. boost/cut +12.0 +14.0 +16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 33 44 55 k w treble control (1) gt control range max. boost/cut +13.0 +14.0 +15.0 db t step step resolution 1 2 3 db speaker attenuators c range control range 70 76 82 db s step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -56db -2 0 2 db v dc dc step adjacent attenuation steps 0 3 mv a mute mute attenuation 80 100 db note1: 1) the device is functionally good at vs = 5v. a step down, on vs, to 4v doest reset the device. 2) bass and treble response: the center frequency and the response quality can be chosen by the external circuitry. TDA7440D 3/16
electrical characteristics (continued.) symbol parameter test condition min. typ. max. unit audio outputs v clip clipping level d = 0.3% 2.1 2.6 v rms r l output load resistance 2 k w r o output impedance 10 30 50 w v dc dc voltage level 3.5 3.8 4.1 v general e no output noise all gains = 0db; bw = 20hz to 20khz flat 515 m v e t total tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db s/n signal to noise ratio all gains 0db; v o = 1v rms ; 95 106 db s c channel separation left/right 80 100 db d distortion a v = 0; v i = 1v rms ; 0.01 0.08 % bus input v il input low voltage 1 v v ih input high voltage 3 v i in input current v in = 0.4v -5 0 5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v 10 m f 5.6nf 100nf 100nf 5.6k 2.2 m f 5.6nf 2.2 m f 100nf 100nf 5.6k 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0.47 m f 0/30db 2db step muxoutl inl volume volume treble treble treble(l) muxoutr inr treble(r) bout(l) spkr att left lout scl sda dig_gnd rout d98au885 i 2 cbus decoder + latches 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 g input multiplexer + gain bass bin(l) bass spkr att right bout(r) bin(r) supply cref agnd v s 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 10 11 19 12 13 23 8 9 18 14 15 r b r b v ref test circuit TDA7440D 4/16
application suggestions the first and the last stages are volume control blocks. the control range is 0 to -47db (mute) for the first one, 0 to -79db (mute) for the last one. both of them have 1db step resolution. the very high resolution allows the implementation of systems free from any noisy acoustical effect. the TDA7440D audioprocessor provides 3 bands tones control. bass stage several filter types can be implemented, connect- ing external components to the bass in and out pins. the fig.1 refers to basic t type bandpass filter starting from the filter component values (r1 in- ternal and r2,c1,c2 external) the centre fre- quency fc, the gain av at max. boost and the fil- ter q factor are computed as follows: f c = 1 2 p ? ```````````````` r1 r2 c1 c2 a v = r2 c2 + r2 c1 + ri c1 r2 c1 + r2 c2 q = ? ``````````````` ` r1 r2 c1 c2 r2 c1 + r2 c2 viceversa, once fc, av, and ri internal value are fixed, the external components values will be: c1 = a v - 1 2 p f c r i q c2 = q 2 c1 a v - 1 - q 2 r2 = a v - 1 - q 2 2 p c1 f c ( a v - 1 ) q treble stage the treble stage is a high pass filter whose time constant is fixed by an internal resistor (25k w typical) and an external capacitor connected be- tween treble pins and ground typical responses are reported in figg. 10 to 13. cref the suggested 10 m f reference capacitor (cref) value can be reduced to 4.7 m f if the application requires faster power on. ri internal c 2 out in c 1 r 2 d95au313 figure 1. figure 2: thd vs. frequency figure 3: thd vs. r load TDA7440D 5/16
figure 4: channel separation vs. frequency figure 6: treble response figure 5: bass response r i = 44k w c9 = c10 = 100nf (bout, bin) r3 = 5.6k w TDA7440D 6/16
i 2 c bus interface data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to posi- tive supply voltage must be connected). data validity as shown in fig. 7, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.8 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 9). the peripheral (audio processor) that ac- knowledges has to pull-down (low) the sda line during this clock pulse. the audio processor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio processor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 7: data validity on the i 2 cbus figure 8: timing diagram of i 2 cbus f igure 9: acknowledge on the i 2 cbus TDA7440D 7/16
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7440D address a subaddress bytes a sequence of data (n byte + acknowledge) a stop condition (p) ack = acknowledge s = start p = stop a = address b = auto increment s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au420 x data subaddress data 1 to data n xxb examples no incremental bus the TDA7440D receives a start condition, the correct chip address, a subaddress with the b = 0 (no incremental bus), n-data (all these data con- cern the subaddress selected), a stop condition. s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au421 xd3 subaddress data xx0 d2 d1 d0 incremental bus the TDA7440D receive a start conditions, the correct chip address, a subaddress with the b = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "xxx1000" to "xxx1111" of data are ignored. the data 1 concern the subaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au422 xd3 subaddress data 1 to data n xx1 d2 d1 d0 TDA7440D 8/16
power on reset condition input selection in2 input gain 28db volume mute bass 0db treble 2db speaker mute data bytes address = 88 hex (addr:open). function selection: first byte (subaddress) msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 x x x b 0 0 0 0 input select x x x b 0 0 0 1 input gain x x x b 0 0 1 0 volume x x x b 0 0 1 1 bass x x x b 0 1 0 0 not used x x x b 0 1 0 1 treble x x x b 0 1 1 0 speaker attenuate "r" x x x b 0 1 1 1 speaker attenuate "l" b = 1: incremental bus active b = 0: no incremental bus x = dont care input selection msb lsb input multiplexer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxx0 0 in4 xxxxxx0 1 in3 xxxxxx1 0 in2 xxxxxx1 1 in1 in incremental bus mode, the "not used" function must be addressed in any case. for example to re- fresh "volume = 0db" and speaker_r = -40db", the following bytes must be sent: subaddress xxx10010 volume data x0000000 bus data xxxx1111 not used data xxxx1111 treble data xxxx1111 speaker_r data x0000010 TDA7440D 9/16
data bytes (continued) input gain selection msb lsb input gain d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 0db 0001 2db 0010 4db 0011 6db 0100 8db 0 1 0 1 10db 0 1 1 0 12db 0 1 1 1 14db 1 0 0 0 16db 1 0 0 1 18db 1 0 1 0 20db 1 0 1 1 22db 1 1 0 0 24db 1 1 0 1 26db 1 1 1 0 28db 1 1 1 1 30db gain = 0 to 30db volume selection msb lsb volume d7 d6 d5 d4 d3 d2 d1 d0 1db steps 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db x 1 1 1 x x x mute volume = 0 to 47db/mute TDA7440D 10/16
data bytes (continued) bass selection msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db treble selection msb lsb treble d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db TDA7440D 11/16
data bytes (continued) speaker attenuate selection msb lsb speaker attenuation d7 d6 d5 d4 d3 d2 d1 d0 1db 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db 0 1 1 0 -48db 0 1 1 1 -56db 1 0 0 0 -64db 1 0 0 1 -72db 1 1 1 1 x x x mute speaker attenuation = 0 to -79db/mute TDA7440D 12/16
20k 20k cref v s d96au430 v s pins: 23 v s d96au434 20 m a rout 24 lout pins: 26, 27 v s d96au426 20 m a v s mixout gnd pins: 8, 10 20 m a v s 100k v ref d96au425 in pins: 1, 2, 3, 4, 5, 6, 7, 28 20 m a v s 33k d96au427 inl inr v ref pins: 19, 11 44k v s bin(r) d96au428 20 m a bin(l) pins: 12, 14 TDA7440D 13/16
50k v s treble(r) d96au433 20 m a treble(l) pins: 18, 19 44k v s bout(r) d96au429 20 m a bout(l) pins: 13, 15 d96au423 20 m a sda pins: 21 d96au424 20 m a scl pins: 20 TDA7440D 14/16
so28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data TDA7440D 15/16
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com TDA7440D 16/16

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